(1) Field of the Invention
The invention relates to a method to form RF devices in an integrated circuit device, and, more particularly, to a method to form metal-insulator-metal (MIM) capacitors and inductors at a chip top level.
(2) Description of the Prior Art
Many types of electronic circuits require relatively large value capacitors and inductors. In particular, radio frequency (RF) circuits are those that function at large frequency levels even above the microwave range. Capacitors and inductors are passive components and are herein called RF devices. These RF devices frequently appear in RF circuits either in integrated form or as individual components.
For integrated circuit devices, the formation of large value capacitors and inductors presents a unique challenge for several reasons. First, these devices can consume large chip areas. Second, there can be interference between the capacitor/inductor and other parts of the circuit. These interactions can cause circuit malfunctions and tend to reduce the linearity of the RF devices. Third, it can be difficult to create devices with a large Q value. Fourth, obtaining precise values is difficult due to process variation.
Referring now to FIG. 1, an exemplary integrated circuit device is shown in cross section. A metal-insulator-metal (MIM) capacitor is formed by a fifth metal level (M5) 18, an insulator layer 22, and a top plate, metal layer 26. The MIM capacitor top plate 26 is coupled to the sixth metal level (M6) 38 through vias 34. A first insulator 14, that may comprise many insulating layers, is shown between the substrate 10 and the capacitor. A second insulator 30 is shown between M518 and M638. In this example, M638 is the top metal level for the process.
By forming the MIM capacitor in an upper metal level, a large capacitor can be constructed without consuming area on the substrate 10 where transistors, not shown, are formed. However, this approach suffers several problems. First, the top plate, metal layer 26 is relatively thin compared to M518 or M638. This is because the fifth via level 34 must couple M638 to M518 or to the top plate metal 26. By limiting the top plate metal 26 thickness, the parasitic resistance increases, and the Q value of the capacitor is reduced. Referring now to FIG. 4, the circuit model for the MIM capacitor is shown. The capacitor value is C 90, the top plate parasitic resistance is RP1 92, and the bottom plate parasitic resistance is RP2 93. Referring again to FIG. 1, note that the top plate 26 is coupled to M638 through vias 34. These vias 34 add significant contact resistance to the top plate parasitic resistance. Second, the capacitor value is limited by area constraints. The M518 and M638 levels are used for circuit connectivity. The capacitor must fit in the unused routing area. Third, there is a significant risk of interference with other circuit signals since the capacitor is formed in the interconnect routing levels M5 and M6.
Referring now to FIG. 2, a top view of an exemplary integrated circuit inductor is shown. An inductor 50 is shown. The inductor 50 is formed as a spiral line comprising M658 and M554. To facilitate interconnection the M5 line 54 is coupled to M658 through the via 60. Referring now to FIG. 3, a cross sectional view of the inductor is shown. Several features should be noted. First, the inductor is formed in the upper metal layers M658 and M554. Next, note that the through metal M554 is coupled using vias 60. In addition, the inductor is formed over a part of the substrate 70 comprising a shallow trench isolation (STI) 74.
Several problems with this approach to forming the inductor should be noted. First, because the current flow through the inductor is parallel to the surface of the substrate 70, the magnetic flux 86 is primarily perpendicular to the surface of the substrate 70. This is why the inductor is fabricated over a part of the integrated circuit where no active devices are formed. Therefore, although the inductor is formed in an upper metal level, it still effectively consumes surface area in the substrate 70. Second, the inductor value is limited by the available surface area. Third, the vias 60 create a significant parasitic resistance that reduces the Q value of the inductor. Referring again to FIG. 4, the circuit model of inductor is shown. The inductor value is given by L 94. The parasitic resistance value is given by RP 97. Finally, a parasitic capacitor value is given by CP 96. Referring again to FIG. 2, this parasitic capacitance is caused by a MIM capacitor created by the interaction between the spiral metal lines 58 and the dielectric 62 therebetween. Fourth, the methods of forming the exemplary spiral inductor and capacitor are not compatible.
Several prior art inventions relate to the manufacture of metal-insulator-metal (MIM) capacitors in integrated circuit devices. U.S. Pat. No. 6,180,976 B1 to Roy discloses a method to form a MIM capacitor where the bottom plate is a damascene line. U.S. Pat. No. 5,895,948 to Mori et al shows a MIM capacitor process. U.S. Pat. No. 5,162,258 to Lemnios et al describes a method to customize a microwave integrated circuit device by incorporating a MIM capacitor. U.S. Pat. No. 5,708,559 to Brabazon et al discloses several methods to form MIM capacitors.
A principal object of the present invention is to provide an effective and very manufacturable method to form radio frequency (RF) devices in an integrated circuit device.
A further object of the present invention is to provide a method to form MIM capacitors having improved parametric performance.
A further object of the present invention is to provide a method to form inductors having improved parametric performance.
Another further object of the present invention is to provide a method to form RF devices producing less interference with other circuits in the integrated circuit device.
Another further object of the present invention is to provide both capacitors and inductors in a top metal layer.
In accordance with the objects of this invention, a method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads.
Also in accordance with the objects of this invention, An integrated circuit device comprising a patterned top metal level overlying a substrate. The top metal level comprises bonding pads, bottom plates for capacitors, and terminals for inductors. A dielectric layer overlies the top metal level. A patterned RF metal level overlies the top metal level. The RF metal level comprises top plates for said capacitors overlying the bottom plates with the dielectric layer therebetween. The RF metal level comprises inductive lines for the inductors.